Semiconductor devices are used for integrated circuits in a variety of electrical and electronic applications, such as computers, cellular telephones, radios, and televisions. One particular type of semiconductor device is a semiconductor storage device, such as a random access memory (RAM) device. RAM devices use an electrical charge to store information. Many RAM devices include many storage cells arranged in a two-dimensional array with two sets of select lines, wordlines and bitlines. An individual storage cell is selected by activating its wordline and its bitline. RAM devices are considered “random access” because any memory cell in an array can be accessed directly if the row and column that intersect at that cell are known.
A commonly used form of RAM is known as a dynamic RAM device. Dynamic random access memory (DRAM) has memory cells with a paired transistor and capacitor. One particular type of DRAM device is a synchronous DRAM (SDRAM) device, in which the memory cells are accessed synchronously. Synchronous dynamic random access memory often takes advantage of the burst mode concept to greatly improve performance by staying on the row containing the requested bit and moving rapidly through the columns. To achieve a high speed operation, a double data rate (DDR) architecture is often used, during which two data transfers are made per clock cycle, one upon the rising edge of the clock and the other upon the falling edge.
A number of techniques have been developed to increase the speed with which data can be read from or written to a memory array. For example, virtual channel SDRAMs are memories in which data of a segment from a memory bank are loaded into a memory channel. The segment is selected from a defined row of the memory bank. After buffer storage in the memory channel, the data are output via an interface via the specification of the column address. The use of the memory channel affords the possibility of buffer-storing data from a memory having a relatively long access time into a buffer memory having a short access time and subsequently outputting them. In this way, on statistical average the data can be read more rapidly from the memory. Power is required to transfer these segments into the channel.
U.S. Pat. No. 5,887,272, which is incorporated herein by reference, discloses an enhanced DRAM that contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of sub arrays, the row registers are located between DRAM sub arrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.
U.S. Pat. No. 5,586,078, which is incorporated herein by reference, discloses a DRAM that includes memory blocks in a form of division of shared sense amplifier configuration in which sub arrays and sense amplifiers serving as cache memories are alternately arranged in the X direction of a memory chip. The memory blocks are arranged in the Y direction. Data lines are formed in parallel with the Y direction for the corresponding sub arrays, for transferring data held in the sense amplifiers corresponding to the sub arrays. I/O pads are arranged in parallel with the X direction, for inputting/outputting data to/from the corresponding sub arrays via the data lines. When the shared sense amplifier configuration and sense amplifier cache system are achieved in a small area of the DRAM, the hit rate of the cache memories is increased, and data can be transferred at high speed by shortening data paths formed in the memory chip.
U.S. Pat. No. 5,528,552, which is incorporated herein by reference, discloses a dynamic random access memory device that causes sense amplifier circuits to serve as a cache memory for sequentially delivering data bits in the sense amplifier circuits, and a row address buffer unit is controlled independently of the sense amplifier circuits so as to change the row address signal without canceling the data bits in the sense amplifier circuits.
U.S. Pat. No. 5,566,118, which is incorporated herein by reference, discloses a dynamic DRAM device including a plurality of memory cell blocks associated with sense amplifier arrays as cache memories, and registers for storing addresses of the memory cell blocks to indicate the contents of the sense amplifiers. A refresh address for a self-refresh mode is sequentially generated to perform a refresh operation upon the memory cell blocks. When the refresh address coincides with a predetermined value, data of the memory cell blocks is read by using an address of one of the registers and is restored in a corresponding sense amplifier array.
U.S. Pat. No. 5,706,244, which is incorporated herein by reference, discloses a semiconductor dynamic random access memory device that has shared sense amplifier units used for not only amplification of data bits but also as a cache storage. A cache system incorporated in the semiconductor dynamic random access memory device individually controls the sense amplifier units to determine whether to allow an access to the selected sense amplifier unit, thereby enhancing the hit ratio.